This is the home of Kactus2, the open source IP-XACT-based tool for ASIC, FPGA and embedded systems design. This and more are brought to you by Tampere University of Technology.

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Important: Kactus2 3.0 is the most thorough revision since the project started. With about 80% of the code lines touched we introduced big architectural changes and a lot of new features to support the new IEEE-1685-2014 IP-XACT standard. All of this gives better IP and Design configurability and adopts the familiar SystemVerilog format for parameters and expressions. We offer a conversion tool upon request for the old IP-XACT XML documents created by previous versions of Kactus2.

IP-XACT Basics

IP-XACT standardises the descriptions of IP-block and design as well as the design flow including integration and configuration information. The scope of IP-XACT covers the IP component library and HW design, and offers placeholders for settings, parameters, options and scripts needed in design automation. It does not specify any language to be used, but XML format to store the information. IP-XACT tools are used for editing and launching other tools for automated operation.


The IP-XACT Component is a central placeholder for all IP information. It defines the interface, parameters, registers/memory areas and some non-functional properties. All these apply to one or more Views that give the implementatin of the IP by source code associated as FileSets. IP-XACT objects are referenced by a VLNV (Vendor,Library, Name,Version) identifier found in the XML file. For this reason the location of the IP-XACT XML file is not significant.


The IP-XACT Design is an assembly of IP-XACT component instances. The components are connected by Bus interfaces that use Bus Definitions. Each component may have parameters and default values, which can be overridden instance by instance as defined in Configurable Element Values. Each design can have different Design Configurations that differ from what View is active in each instance.


IP-XACT supports infinite levels of hierarchy as depicted in the Figure below. The key idea is that any IP-XACT component is independently re-usable at any level of design hierarchy. For this reason the propagation of parameters is basically limited to one level of hierarchy through CEVs, but tools can offer similar propagation mechanisms as in legacy HDLs.


A simplified IP-XACT design flow is depicted in the Figure below. Generators produce top-level HDL code for synthesis and project files for collecting included HDL code from the components. Generators are often used to create HW dependent SW code, e.g. header files for the registers.


Kactus2 scope on IP-XACT

Kactus2 includes tools for all essential parts of the IP-XACT design flow. Import wizards are used to create IP-XACT models from legacy VHDL and Verilog code, and generators are used to create source code for simulation, synthesis and SW development.


Legacy HDL code import to IP-XACT (VHDL, Verilog)

Kactus2 import wizard searches for the VHDL entity and extracts the ports. Parameters are extracted from the generics, and constants found in packages. Kactus2 writes this information to the IP-XACT component XML file. The source files are referenced by the path and name in the XML file.


HDL code generation from IP-XACT (VHDL, Verilog)

Kactus2 VHDL generator creates the top entity for the IP-XACT Design that instantiates the component entities. The Component entities can also be (re)generated from the IP-XACT Component, especially if there is only the IP-XACT description without any imported HDL files.



Kactus2 guides towards faultless IP and design data exchange

Kactus2 offers best of class usability that helps communication between HW and SW designers, customers and subcontractors and between managers and developers. Graphical designs views help explain the product architecture and contribute to requirements. Kactus2 allows combination of drafted and fully specified IPs at the same design. All have the freedom to propose new blocks and try out different alternatives, while all data is formalized and manual copying of data eliminated.

Kactus2 can be fitted to current design flows. Basically there's no need to change code development, synthesis, verification or other critical tools, but the way of configurations might need changes. Import wizards help creating IP -XACT models from existing VHDL and Verilog IPs. Generators produce synthesisable code for the RTL flow.

You don't lock-in with Kactus2, because you own data and can freely access it at any time. Kactus2 is based on IEEE1685/IP-XACT metadata with our free and open extensions. Kactus2 comes with a core for managing components and designs plus plugins for automation.


To whom

Small and mid-size vendor and integrator companies that now have only the traditional toolset: office tools (doc, xls, ppt) for specification/documentation and Verilog/VHDL, C/C++, FPGA tools for designs. Kactus2 helps taking a step to metadata based design that keeps products much better manageable while still using also the familiar tools.

Universities and research laboratories that implement new content (IP bocks, SW modules). Kactus2 helps packetizing the content in a standard way for (re)using it much easier by others, specifically when the original contributor leave after e.g. a PhD project.

Bigger companies and tool providers that already have modern design tool flows and resources for developing higher abstraction methods. Kactus2 offers a great R&D environment for trying new methodology ideas and user interface innovations.

HW/SW mapping

What you can do with Kactus2

Kactus2 flow

Draft & Specify from scratch

  • Quickly draft block diagram blueprints for product boards (PCB), chips, system-on-chip, IPs and get them stored in IP-XACT format
  • Draft communication channel abstraction endpoint design for all processors and fixed IPs in a product
  • For new IP-blocks generate code templates (VHDL entities, headers) from IP-XACT components defined in Kactus2
kactus2 drafting

Packetize IP for reuse and exchange

  • Create "electronic datasheets" of your existing IPs for library as templates and blocks ready for integration
  • Import, export and integrity check IP libraries from any standard compatible IP vendor
    Kactus2 SW import wizard finished
  • Analyze file dependencies between IP's source files and easily see changes in any file
Kactus2 dependency analyzer

Create MP-SoC products

  • Create HW designs with hierarchy across PCB, Chip, SoC, IP-blocks
  • Define memory areas and registers for the components
    Kactus2 memory visualization
  • Configure base addresses
    Kactus2 address editor
  • Create system designs that map SW to HW
  • Create SW architecture with communication abstraction as channels (MCAPI, Socket and others)
  • Configure all designs
  • Generate everything ready for HDL synthesis and SW build for all processors
    Kactus2 memory header generator

What you can't do with Kactus2

  • Create IP functionality. You should use HDL editors and SW IDEs. Kactus2 can create stub code for interfaces. For HW components you may use e.g. TCE-tools to create "C to VHDL" so you can create the copmponent source without knowing much of HDLs.
  • Generate binaries/executables. You should use HDL synthesis and SW compilation tools, but there is clear path from Kactus2 to other tools. IP-XACT generators are the standard way to build automation between tools.
  • Press money. But you save a lot of time and effort.

What is Metadata?

Kactus2 follows the general platform based design paradigm with extensive use of metadata. Product is created by assembling application components on platforms, and all are packetized to a library with metadata. Metadata makes sure unambiguous interoperability between partners and tools and makes design automation possible.

Metadata for a component is formal, vendor and technology independent description of the component. It includes references to source files and other related information. Components are in practice HW blocks and SW codes in different abstraction and granularity levels.

Metadata for a design is a formal structural description. It includes references to component metadata, tools, configurations and other design related information.

In brief, metadata is like an electronic datasheet + product + project documentation.Read more on our white paper or presentation on MeCoES'12 workshop.

What is metadata based design flow?

First, components are encapsulated and separated from their source, e.g. HDL source code is embedded via links to the source file in the metadata file. IP metadata is used to assemble compopnents in a design. IPs as well as the design itself may have generic parameters, which are configured using generators that are typically scripts. The final configured design can be seen as "instructions" on how to create the final executables.


Metadata benefits

  • Metadata-based design flow makes selling, buying, integrating and reusing IPs and complete designs much less error prone
  • Saves time and effort when managing several configurations and variants of the products
  • Machine readable documentation also for the tools, languages and environments for backup and maintenance
  • Increased design automation and standard compatibility

Kactus2 extensions to IP-XACT

We handle also SW components as IP-XACT objects. This allows building dependencies and reusing SW easier. IP-XACT parameters and vendor extensions are utilized.
We add attributes to help managing the design process from re-usable components and designs to fixed product releases. IP-XACT parameters and vendor extensions are utilized.
Product hierarchy

Embedded system products consists of HW and SW design data and plenty of process and other auxiliary information. We consider the product as a hierarchy of its physical realization. Environments refer to the context in which products are specified, verified, tested and finally used. Each product level include associated information like documentation, source codes, tools, configurations and production data.

Our product hierarchy model consists of boards containing chips that are fixed-function or they can accommodate a system-on-chip (SoC), which are built up from IP-blocks. All levels include both HW and SW related information.

The scope of IEEE1685/IP-XACT is on the IP and SoC levels, but we apply the standard also to other levels, aiming at product level information management (PDM, product data management).


Summary of past milestones

Kactus2 roadmap


Example designs

Multicore Association MCAPI implementation and demo for PC and ARM

A demo includes VirtualBox Lubuntu image (1.2GB) including the following:

  • POSIX-based MCAPI implementation PMQ-MCAPI
  • Demo projects for PC and Altera Cyclone V FPGA-SoC ARM ready to launch
  • Linux build for ARM
  • Kactus2 libraries for the demos
  • Kactus2, compilers etc. to get it up and running with zero configuration

Read instructions,documentation and get PMQ-MCAPI open source code.

Download image

Alternatively you may download only Kactus2 library (3.1MB) containing the demo projects.

Download Kactus2 library

Quick guide to open Kactus2 library

  • Download MCAPI demo Kactus2 library and unzip it to a working folder
  • Download Kactus2 and install it
  • Open Kactus2 -> Configure library -> Add the path to the working library where you unzipped the MCAPI Kactus2 library package Setting_directories_for_Kactus2_library.png
  • Browse the project on left. You may open the System design that shows MCAPI channels designed in Kactus2

Kactus2 Publications


An introduction to IP-XACT and Kactus2 presentation at ORCONF2015, Oct 9-11 at CERN

Learn about VLNV and Kactus2 library

Kactus2 keyboard shortcuts

Usual shortcuts for editing
ctrl-tab, ctrl-shift-tab
Move left/right of the design view tabs
When dragging from library, drop to replace the component in design. When dragging within design, switch dropped component
Open (table cell) for editing


Tutorial on exporting pin definitions from QuartusII to Kactus2, creating IP-XACT bus interfaces and port maps and generating from Kactus2 the PADS Logic decals for PCB design


Getting started for the first time with existing libraries
  • Basics of docking windows and customizing workspaces
  • Adding new libraries
  • Filtering library items and browsing either VLNV name based or product hierarchy that is based on VLNV references from top down


A use case how to specify a new IP-XACT metadata component in Kactus2 for a new hardware IP-block (non-existing)
  • Create Port definitions
  • Create Model Parameters (for VHDL generics)
  • Define local Memory areas and registers for this component (IP-XACT Memory Map Definition)
  • Create bus interfaces and port maps, this is skipped in the demo
  • Generate VHDL stub for the IP-block implementation


A use case how to create IP-XACT HW-Design and generate from it C header, Altera Quartus project and Top VHDL

  • Add new IP-block to existing design
  • Set base addresses in HW design
  • Generate top-level VHDL
  • Generate Quartus II project
  • Generate C header files


All the information and any part thereof provided on this website are provided « AS IS » without warranty of any kind either expressed or implied including, without limitation, warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property rights.

TUT makes no representations or warranties as to the accuracy or completeness of any materials and information incorporated thereto and contained on this website. TUT makes no representations or warranties that access to this website will be uninterrupted or error-free, that this website (the materials and/or any information incorporated thereto) will be secure and free of virus or other harmful components.

Contact us

We welcome any feedback from the tools and suggestions to new features. Further directions are:

About us

We are a research group in the Department of Pervasive Computing at Tampere University of Technology. We are rooted in hardware, from parallel processor boards to System-on-Chip architectures. Aligned to that we have a strong track record on design methodologies and tools development, as well as video encoders as a major application domain

Today we focus on improving the productivity of SoC and embedded system design. The means are language and tool agnostic metadata to support re-use and optimization of the design workflow. New ideas are brought into life in our tools that have superior usability as the first requirement.

We work on close collaboration with companies to get requirements for the research and feedback on our solutions. Please contact us if you are interested in a joint project.

The Team

Current members (Updated Nov 27 2015) are Prof. Timo D. Hämäläinen, Dr. Jarno Vanne, Esko Pekkarinen, Sakari Lahti, Janne Virtanen, Panu Sjövall.
Alumni are Dr. Erno Salminen, Dr. Kimmo Kuusilinna, Dr. Pasi Kolinummi, Dr. Tero Kangas, Dr. Panu Hämäläinen, Dr. Vesa Lahtinen, Dr. Ari Kulmala, Dr. Tero Arpinen, Dr. Petri Kukkala, Dr. Marko Hännikäinen, Lauri Matilainen, Mikko Honkonen, Timo Korpela, Joni-Matti Määttä, Antti Kamppi, Juha Arvio, Juuso Järvinen, Jussi Nieminen, Tapio Koskinen, Mikko Setälä, Kalle Holma, Timo Alho, Antti Rasmus, Janne Muhonen, Pasi Liimatainen, Ville-Veikko Jokinen, Marjo Kari, Pasi Pulkkinen, Kimmo Tikkanen, Eero Ryytty, Antti Jore, Aki Launiainen, Timo Kaikumaa, Juha Särkijärvi, Miia Viitanen, Kaisa Haapala, Tomi Sokeila.



Some past projects

Archived Funbase-project site