This is the home of Kactus2, the open source IP-XACT-based tool for ASIC, FPGA and embedded systems design. This and more are brought to you by Tampere University of Technology.
IP-XACT standardises the descriptions of IP-block and design as well as the design flow including integration and configuration information. The scope of IP-XACT covers the IP component library and HW design, and offers placeholders for settings, parameters, options and scripts needed in design automation. It does not specify any language to be used, but XML format to store the information. IP-XACT tools are used for editing and launching other tools for automated operation.
The IP-XACT Component is a central placeholder for all IP information. It defines the interface, parameters, registers/memory areas and some non-functional properties. All these apply to one or more Views that give the implementation of the IP by source code associated as FileSets. IP-XACT objects are referenced by a VLNV (Vendor,Library, Name,Version) identifier found in the XML file. For this reason the location of the IP-XACT XML file is not significant.
The IP-XACT Design is an assembly of IP-XACT component instances. The components are connected by Bus interfaces that use Bus Definitions. Each component may have parameters and default values, which can be overridden instance by instance.
IP-XACT supports infinite levels of hierarchy as depicted in the Figure below. A component is hierarchical when it includes a design, which includes instance(s) of other component(s). Any IP-XACT component should be independently re-usable at any level of design hierarchy, but it is still possible to propagate parameter values down in hierarchy.
IP-XACT helps describing many variations of the component. Parameters are used to define configurable things in many IP-XACT elements (the component itself). The component can have several implementations, each defined in Component Instantiations e.g. Verilog, VHDL and SystemC. Module parameters are implementation language specific parameters. Module and other parameters can refer to each other. A hierarchical component can have different designs defined in Design Instantiations or a design that has different configurations defined in Design Configuration Instantiations.
Views are collections of the Instantiations for some specific design purpose like high-level modeling, verification or releasing a product. We call them "mission configurations" to separate them from Instantiations that are "implementation configurations". A component can have all instantiation types, but Views tell what of them are used in each case.
IP-XACT designs can be configured in two principal ways: by different parameter values or by different Views for component instances. Each setup is stored in a Design Configuration, each of which refers to the same Design. Parameters can be propagated down in hierarchy as follows. The parameters and Module Parameters that are defined to be configurable in Component Instances are seen as Configurable Element Values (CEV) in the Design. The CEV can be set to a fixed value or to refer to other parameter e.g. at the upper hierarchy. Design Configurations are handy to define different sets of the CEVs
A simplified IP-XACT design flow is depicted in the Figure below. Generators produce top-level HDL code for synthesis and project files for collecting included HDL code from the components. Generators are often used to create HW dependent SW code, e.g. header files for the registers.
Kactus2 includes tools for all essential parts of the IP-XACT design flow. Import wizards are used to create IP-XACT models from legacy VHDL and Verilog code, and generators are used to create source code for simulation, synthesis and SW development.
Kactus2 import wizard searches for the VHDL entity and extracts the ports. Parameters are extracted from the generics, and constants found in packages. Kactus2 writes this information to the IP-XACT component XML file. The source files are referenced by the path and name in the XML file.
Kactus2 VHDL generator creates the top entity for the IP-XACT Design that instantiates the component entities. The Component entities can also be (re)generated from the IP-XACT Component, especially if there is only the IP-XACT description without any imported HDL files.
Kactus2 offers best of class usability that helps communication between HW and SW designers, customers and subcontractors and between managers and developers. Graphical designs views help explain the product architecture and contribute to requirements. Kactus2 allows combination of drafted and fully specified IPs at the same design. All have the freedom to propose new blocks and try out different alternatives, while all data is formalized and manual copying of data eliminated.
Kactus2 can be fitted to current design flows. Basically there's no need to change code development, synthesis, verification or other critical tools, but the way of configurations might need changes. Import wizards help creating IP -XACT models from existing VHDL and Verilog IPs. Generators produce synthesisable code for the RTL flow.
You don't lock-in with Kactus2, because you own data and can freely access it at any time. Kactus2 is based on IEEE1685/IP-XACT metadata with our free and open extensions. Kactus2 comes with a core for managing components and designs plus plugins for automation.
Small and mid-size vendor and integrator companies that now have only the traditional toolset: office tools (doc, xls, ppt) for specification/documentation and Verilog/VHDL, C/C++, FPGA tools for designs. Kactus2 helps taking a step to metadata based design that keeps products much better manageable while still using also the familiar tools.
Universities and research laboratories that implement new content (IP bocks, SW modules). Kactus2 helps packetizing the content in a standard way for (re)using it much easier by others, specifically when the original contributor leave after e.g. a PhD project.
Bigger companies and tool providers that already have modern design tool flows and resources for developing higher abstraction methods. Kactus2 offers a great R&D environment for trying new methodology ideas and user interface innovations.
Draft & Specify from scratch
Packetize IP for reuse and exchange
Create MP-SoC products
Kactus2 follows the general platform based design paradigm with extensive use of metadata. Product is created by assembling application components on platforms, and all are packetized to a library with metadata. Metadata makes sure unambiguous interoperability between partners and tools and makes design automation possible.
Metadata for a component is formal, vendor and technology independent description of the component. It includes references to source files and other related information. Components are in practice HW blocks and SW codes in different abstraction and granularity levels.
Metadata for a design is a formal structural description. It includes references to component metadata, tools, configurations and other design related information.
First, components are encapsulated and separated from their source, e.g. HDL source code is embedded via links to the source file in the metadata file. IP metadata is used to assemble compopnents in a design. IPs as well as the design itself may have generic parameters, which are configured using generators that are typically scripts. The final configured design can be seen as "instructions" on how to create the final executables.
Our product hierarchy model consists of boards containing chips that are fixed-function or they can accommodate a system-on-chip (SoC), which are built up from IP-blocks. All levels include both HW and SW related information.
The scope of IEEE1685/IP-XACT is on the IP and SoC levels, but we apply the standard also to other levels, aiming at product level information management (PDM, product data management).
A demo includes VirtualBox Lubuntu image (1.2GB) including the following:
Alternatively you may download only Kactus2 library (3.1MB) containing the demo projects.Download Kactus2 library
A use case how to create IP-XACT HW-Design and generate from it C header, Altera Quartus project and Top VHDL
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We are a research group in the Department of Pervasive Computing at Tampere University of Technology. We are rooted in hardware, from parallel processor boards to System-on-Chip architectures. Aligned to that we have a strong track record on design methodologies and tools development, as well as video encoders as a major application domain
Today we focus on improving the productivity of SoC and embedded system design. The means are language and tool agnostic metadata to support re-use and optimization of the design workflow. New ideas are brought into life in our tools that have superior usability as the first requirement.
We work on close collaboration with companies to get requirements for the research and feedback on our solutions. Please contact us if you are interested in a joint project.
Current members (Updated Apr 1 2016) are
Prof. Timo D. Hämäläinen,
Dr. Jarno Vanne,
Esko Pekkarinen, Sakari Lahti, Janne Virtanen, Panu Sjövall, Arto Oinonen.
Alumni are Dr. Erno Salminen, Dr. Kimmo Kuusilinna, Dr. Pasi Kolinummi, Dr. Tero Kangas, Dr. Panu Hämäläinen, Dr. Vesa Lahtinen, Dr. Ari Kulmala, Dr. Tero Arpinen, Dr. Petri Kukkala, Dr. Marko Hännikäinen, Lauri Matilainen, Mikko Honkonen, Timo Korpela, Joni-Matti Määttä, Antti Kamppi, Juha Arvio, Juuso Järvinen, Jussi Nieminen, Tapio Koskinen, Mikko Setälä, Kalle Holma, Timo Alho, Antti Rasmus, Janne Muhonen, Pasi Liimatainen, Ville-Veikko Jokinen, Marjo Kari, Pasi Pulkkinen, Kimmo Tikkanen, Eero Ryytty, Antti Jore, Aki Launiainen, Timo Kaikumaa, Juha Särkijärvi, Miia Viitanen, Kaisa Haapala, Tomi Sokeila.